FIG. 1 shows a schematic block diagram of an LDO (low-dropout) linear voltage regulator (100) with high power supply rejection (PSR). The LDO linear voltage regulator is commonly referred to as simply “LDO.” As shown in FIG. 1, the feedback network (101), including a resistor divider and an error amplifier (102), regulates the DC output voltage Vout to a desired level given by Vout=Vref*(1+R1/R2). The error amplifier (102) may be a single stage or a multi-stage amplifier. The resistor R1 may be a short circuit, and the resistor R2 may be an open circuit in some architectures. The pass transistor Mpass may be either a field effect transistor (FET) or a bipolar transistor, and may be of either n-type or p-type. Multi-stage and high-gain amplifiers are typically used as the implementation of the error amplifier (102) in the feedback network (101). Cext (104) represents a physical off-chip external capacitor, and CL (105) represents the load capacitance (without including Cext). The supply rejection block (103) is used to enhance the power supply rejection of the LDO (100). LDO architectures are generally categorized into two main categories: LDOs that requires an external capacitor and LDOs that do not require an external capacitor.
Architectures that require external capacitor to guarantee the stability of the LDO usually have superior performance over the other type. These performance parameters include both superior power supply rejection (PSR) and load transient regulation. Power supply rejection is the ability of the LDO to reject any noise coming from the supply through the Vin terminal in FIG. 1. Throughout this disclosure, the terms, “power supply,” “supply,” “VIN,” and “VIN terminal” may be used interchangeably to refer to the power source input to a voltage regulator. Further, load transient regulation is the change in the output voltage Vout when there is an instantaneous change in the load current, IL. In prior art, LDOs that use external capacitor achieve PSR of around 56 dB at 10 MHz, and load transient regulation of less than 10 mV when the load current changes from 1 to 100 mA in 1 μsec (with an external capacitance higher than 1 μF). The external capacitor is usually any capacitor that cannot be implemented on the same chip where the LDO is implemented.
On the other hand, LDOs that do not require an external capacitor are referred to as capacitor-less LDOs. Generally, the capacitor-less LDOs use on-chip capacitors. The main advantage of the capacitor-less implementation is that it does not require an external capacitor. This helps to reduce the cost of any device that uses this LDO. Capacitor-less LDOs are used to supply power to multiple circuits inside Systems-On-a-Chip (SOCs) and microprocessors, including embedded memories, PLLs, DLLs and high-speed interfaces. The main drawback of this architecture is that both PSR and load transient regulation are much worse than LDOs using external capacitors. Prior art designs reported PSR worse than 50 dB at 1 MHz, and load transient regulation worse than 1V when the load current changes from 1 to 200 mA in 1 μsec. Increasing the load current makes these two parameters even worse. Prior art designs show that increasing the maximum current to 500 mA makes the PSR to be worse than 30 dB at 1 MHz. These two performance parameters show that the capacitor-less LDO cannot be used in many applications that require superior performance of PSR and load transient regulation.
FIG. 2 shows a schematic block diagram of a capacitor-less LDO (200) with high PSR (based on the supply rejection block (203)). As noted above, a capacitor-less LDO (200) has degraded performance comparing to the LDO (100) shown in FIG. 1. The reason for the degraded performance is that the capacitor-less LDO (200) requires that the dominant pole of the open loop transfer function be placed in the feedback network (201), e.g., via the second stage amplifier (204) with the miller capacitor Cm shown in FIG. 2. This technique is widely applied in many capacitor-less LDO such as the work done by Dow et. al. (U.S. Pat. No. 7,512,909) and Castelli, et. al. (U.S. Pat. No. 6,300,749). Generally, the prior art implementations of capacitor-less LDOS place this dominant pole in the feedback loop. Placing the dominant pole in the feedback loop at the output of the error amplifier (202) makes the LDO (200) slower, and thus it does not react fast enough to the load transient variations and the input line variations. In addition, a zero that depends on the load current must be implemented to support a wide range of DC load currents. Possible implementations were shown by Castelli, et. al. (U.S. Pat. No. 6,300,749), and Gregorius (U.S. Pat. No. 6,700,361 B2). Another drawback of placing the dominant pole in the feedback loop is that this limits the performance of capacitor-less LDOs. For example, the best PSR and load transient regulation that capacitor-less LDOs can achieve, such as the capacitor-less LDO (200), are typically limited to about 40 dB at 1 MHz, and 1V for a step in the load current of 200 mA in 1 μsec, respectively. Another drawback of many existing capacitor-less LDOs is that they cannot support capacitor loads from 0 to 10 micro-Farad (μF). Prior art capacitor-less LDOs typically become unstable (e.g., the LDO output would oscillate) if the output capacitor exceeds 1 nano-Farad (nF). On the contrary, prior art LDOs that require external capacitor cannot be used when the load capacitance is lower than 0.1 μF (e.g., the LDO output would oscillate). Accordingly, there is a need for an LDO that can support a wide range of load capacitance values ranging from 0 to 10 μF and load resistances ranging from infinity to the maximum allowed current.
The load switch regulator has substantially the same structure as the LDO voltage regulator. The main difference between the LDO and the load switch regulator is the reference voltage (Vref). In the case of LDO voltage regulator, Vref is supply independent and usually generated from a bandgap reference voltage circuit. In the case of the load switch regulator, Vref is a scaled (and filtered) version of the DC value of the supply. Thus, the DC level of the output voltage Vout changes proportionally with the DC level of the input voltage V. Accordingly, the block diagrams shown in FIGS. 1 and 2 may also be used to represent a load switch regulator with external capacitor and a capacitor-less load switch regulator, respectively. Similar to the capacitor-less LDO voltage regulators, capacitor-less load switch regulators have a limited PSR and load transient regulation of about 50 dB at 1 MHz, and 1V for a step in the load current of 200 mA in 1 μsec, respectively. Throughout this disclosure, the terms “load switch regulator,” “load switch linear voltage regulator,” and “load switch” may be used interchangeably. Further, the term “LDO/load switch linear voltage regulator” refers to either an LDO or a load switch depending on specific configurations of the reference voltage used.